AI Designing AI Chips: How Agentic and ML Tooling Is Changing Place-and-Route, Verification, and EDA

There is a tidy story that AI now designs the chips that run AI. The reality is more interesting and more bounded. Machine learning and, more recently, agentic tooling have moved into real parts of the chip-design flow and are delivering measurable gains, but they cluster in the places where the output can be checked, and they stay out of the places where it cannot. Understanding that line is the whole story.

A quick map of the flow

Designing a chip runs from architecture to register-transfer level (RTL) code, through logic synthesis, floorplanning, placement, clock-tree and routing, timing closure, physical verification, and finally signoff and tapeout. The software that drives all this is EDA (electronic design automation), dominated by Synopsys, Cadence, and Siemens. It is compute-heavy, deeply iterative, and expensive in both tool licenses and engineer-hours.

Where ML already helps: place-and-route and search

The most mature use is in physical design, optimising power, performance, and area (PPA). Tools like Synopsys DSO.ai and Cadence Cerebrus use reinforcement learning to drive the many knobs of place-and-route toward better PPA with far less manual iteration, and Google published reinforcement-learning floorplanning in Nature. These are real, deployed, and measurable: better PPA, and weeks of senior-engineer time saved per design.

The reason it works here is that the goal is quantifiable. A layout that meets timing and hits an area target is objectively good, so an optimiser can be pointed at a clear reward. The same is true of design-space exploration: ML can search enormous configuration spaces faster than brute force because every candidate can be scored.

Verification: the largest, least glamorous bottleneck

The biggest cost in a chip project is usually not design, it is verification: proving the RTL actually does what the spec says, and closing coverage (hitting every state and corner case). It routinely consumes more than half of total effort. It is also unusually well suited to LLMs, because so much of it is language-adjacent: reading specs, writing testbenches and assertions, triaging coverage holes, and making sense of failure logs. NVIDIA’s ChipNeMo work is an early sign of domain-tuned models pointed squarely at this.

Agentic workflows, and the trust problem

The frontier is agentic: systems that can run the EDA flow, propose RTL changes, write tests, and iterate on PPA with limited supervision. The hard constraint is trust. A tapeout costs millions of dollars and months of calendar time, and a missed bug can be catastrophic and unfixable in shipped silicon. So nothing reaches signoff on a model’s say-so; it has to pass formal checks, coverage, and human review.

What full-stack designers see that vendors miss

Two things get lost in the hype. First, the gains are real but bounded by the checkable-output principle: AI accelerates the parts of the flow with an objective score and stalls where correctness is subjective or catastrophic to get wrong. “AI designs chips end to end” overstates the autonomy by a wide margin. Second, there is a genuine flywheel: better AI chips give more compute, which builds better AI tools for designing chips, which yield better chips. But the flywheel turns at the speed of verification and physics, not at the speed of model releases.

The takeaway

AI is already a serious force in chip design, concentrated in PPA optimisation and, increasingly, verification, the places where its work can be measured and checked. Treat claims of autonomous, end-to-end chip design with skepticism, and treat steady gains in engineer productivity and PPA as the real, compounding story. Knowing which is which requires having stood inside the flow, which is exactly the vantage point we bring.